\doxysection{OCTOSPI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_o_c_t_o_s_p_i___type_def}{}\label{struct_o_c_t_o_s_p_i___type_def}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}


OCTO Serial Peripheral Interface.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ac71d27abd195793719c5a5991191e8a4}{CR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ab4a777b2a2635f47a26ab4328e8d4a85}{RESERVED}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ad55538f7543126fa1fdb2d0ad9d75849}{DCR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a961f31cc49d83c8e42550eb21d9c8a61}{DCR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ae7e093d03f39bff4c59db5ea5132dabb}{DCR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a236b297d03ff9b84c6ac71e18b09e4f1}{DCR4}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a1396a146e3c22be923626d604bbce470}{RESERVED1}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_af2d07941b01f96222d175a411a99cbc5}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_aa542fba306d6f4fca93c83155901e5f9}{FCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_af8fcdc41ec1e2b222e804dab9970cd10}{RESERVED2}} \mbox{[}6\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a18bbd693bea6be022533707df2438fdc}{DLR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a4e57b705fa76a5e8a671d5cbb31e2da8}{RESERVED3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a2afc2358d015b00bdc9ae1d19775fc39}{AR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a03509b1d3c60ccbb7d1cde25b08fcce8}{RESERVED4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_af349e5d2d8db8719023ed2109676f720}{DR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_af6839968188cfe826d6672fad77e7be4}{RESERVED5}} \mbox{[}11\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_aceec86c14c2af88f8c441a23d27c0c22}{PSMKR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a1c1eea519097a483369b16d579213b21}{RESERVED6}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a1bb4b32c85c7d4a2c52dd12fb9fbc8e3}{PSMAR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a63540ebe30220332fd765f775ffd0aa0}{RESERVED7}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ac4d100c3a19d687362814b9975f61db5}{PIR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a534fdd219a20c191e0a451b1b164ee1c}{RESERVED8}} \mbox{[}27\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a3fa9d712bb263f5e5138df69b2e3bd00}{CCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_aff35db3f551e942d4701624c14554afb}{RESERVED9}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_abd076236680eeed099c89f7443e23880}{TCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ab273fcbf40893bb4f213f9c3991a7f86}{RESERVED10}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a05ea31567da177f80d31e822bd555e8b}{IR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a6027570a8b87a6843d69209f5e08c759}{RESERVED11}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_acbda2c2cf5374ccfd85f0c59490fe14a}{ABR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a8a7c7b5da8ab25a785528330a2930d3f}{RESERVED12}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a6b37c4aeb2d2b387fb79a6af2454d8d3}{LPTR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a41c9fec3b5915ebb84e0c65bd0f6112c}{RESERVED13}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a49e9d597b1d04c06107e6f458a893494}{WPCCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a4297eefcc58cebb4137aa7aa8b3273e8}{RESERVED14}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_acc4f24b481b265e2b9e1de1cdbcc7010}{WPTCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a684105027411e5937275840c83618729}{RESERVED15}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ac83773556b0dc04b2a3bda3820e1a258}{WPIR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_aa4f4afe2981ea4f9516428393ffc3b0e}{RESERVED16}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ac5f058bd9896d8bfc4fa3206d1e1f755}{WPABR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a9af5040cff1d5d7cc881da5cf9da79bc}{RESERVED17}} \mbox{[}7\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a72e85208b55696102636bdf50e58dc98}{WCCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a50e4dd6d85fc5aa3d157c6d101da2ae8}{RESERVED18}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a8386b6515a1abf5b6c01506469779695}{WTCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a5f9bb07a7f90f6c9629f2c8a0cbcd2ad}{RESERVED19}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_afd4ca0392882475e1d8ff0461d97362e}{WIR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a4454cd7801f08e319b93153efe6dffa4}{RESERVED20}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a5f2343ad009c5df8a20651333a26da6d}{WABR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_afb0d39d49dab12fb3db244623f8ac0c9}{RESERVED21}} \mbox{[}23\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a6ad289f43ae45a78a69c5eabce275287}{HLCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a17106bf864619eeb7a9f670e1882681a}{RESERVED22}} \mbox{[}122\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_aef9bc968c5d50c955027702a8a687de7}{HWCFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_adad6a0a30021b2b7277d2ab520767e25}{VER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_a4cde4c505402e2ebb6775f602d859116}{ID}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_o_c_t_o_s_p_i___type_def_ae83a4795255896d4a015d3526b7df762}{MID}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
OCTO Serial Peripheral Interface. 

\label{doc-variable-members}
\Hypertarget{struct_o_c_t_o_s_p_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_o_c_t_o_s_p_i___type_def_acbda2c2cf5374ccfd85f0c59490fe14a}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!ABR@{ABR}}
\index{ABR@{ABR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ABR}{ABR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_acbda2c2cf5374ccfd85f0c59490fe14a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+ABR}

OCTOSPI Alternate Bytes register, Address offset\+: 0x120 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a2afc2358d015b00bdc9ae1d19775fc39}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!AR@{AR}}
\index{AR@{AR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AR}{AR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a2afc2358d015b00bdc9ae1d19775fc39} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+AR}

OCTOSPI Address register, Address offset\+: 0x048 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a3fa9d712bb263f5e5138df69b2e3bd00}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!CCR@{CCR}}
\index{CCR@{CCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR}{CCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a3fa9d712bb263f5e5138df69b2e3bd00} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+CCR}

OCTOSPI Communication Configuration register, Address offset\+: 0x100 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ac71d27abd195793719c5a5991191e8a4}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!CR@{CR}}
\index{CR@{CR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ac71d27abd195793719c5a5991191e8a4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+CR}

OCTOSPI Control register, Address offset\+: 0x000 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ad55538f7543126fa1fdb2d0ad9d75849}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DCR1@{DCR1}}
\index{DCR1@{DCR1}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCR1}{DCR1}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ad55538f7543126fa1fdb2d0ad9d75849} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DCR1}

OCTOSPI Device Configuration register 1, Address offset\+: 0x008 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a961f31cc49d83c8e42550eb21d9c8a61}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DCR2@{DCR2}}
\index{DCR2@{DCR2}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCR2}{DCR2}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a961f31cc49d83c8e42550eb21d9c8a61} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DCR2}

OCTOSPI Device Configuration register 2, Address offset\+: 0x00C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ae7e093d03f39bff4c59db5ea5132dabb}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DCR3@{DCR3}}
\index{DCR3@{DCR3}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCR3}{DCR3}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ae7e093d03f39bff4c59db5ea5132dabb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DCR3}

OCTOSPI Device Configuration register 3, Address offset\+: 0x010 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a236b297d03ff9b84c6ac71e18b09e4f1}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DCR4@{DCR4}}
\index{DCR4@{DCR4}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCR4}{DCR4}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a236b297d03ff9b84c6ac71e18b09e4f1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DCR4}

OCTOSPI Device Configuration register 4, Address offset\+: 0x014 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a18bbd693bea6be022533707df2438fdc}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DLR@{DLR}}
\index{DLR@{DLR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DLR}{DLR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a18bbd693bea6be022533707df2438fdc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DLR}

OCTOSPI Data Length register, Address offset\+: 0x040 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_af349e5d2d8db8719023ed2109676f720}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!DR@{DR}}
\index{DR@{DR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_af349e5d2d8db8719023ed2109676f720} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+DR}

OCTOSPI Data register, Address offset\+: 0x050 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_aa542fba306d6f4fca93c83155901e5f9}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!FCR@{FCR}}
\index{FCR@{FCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FCR}{FCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_aa542fba306d6f4fca93c83155901e5f9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+FCR}

OCTOSPI Flag Clear register, Address offset\+: 0x024 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a6ad289f43ae45a78a69c5eabce275287}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!HLCR@{HLCR}}
\index{HLCR@{HLCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HLCR}{HLCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a6ad289f43ae45a78a69c5eabce275287} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+HLCR}

OCTOSPI Hyperbus Latency Configuration register, Address offset\+: 0x200 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_aef9bc968c5d50c955027702a8a687de7}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!HWCFGR@{HWCFGR}}
\index{HWCFGR@{HWCFGR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HWCFGR}{HWCFGR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_aef9bc968c5d50c955027702a8a687de7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+HWCFGR}

OCTOSPI HW Configuration register, Address offset\+: 0x3\+F0 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a4cde4c505402e2ebb6775f602d859116}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!ID@{ID}}
\index{ID@{ID}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ID}{ID}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a4cde4c505402e2ebb6775f602d859116} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+ID}

OCTOSPI Identification register, Address offset\+: 0x3\+F8 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a05ea31567da177f80d31e822bd555e8b}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!IR@{IR}}
\index{IR@{IR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IR}{IR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a05ea31567da177f80d31e822bd555e8b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+IR}

OCTOSPI Instruction register, Address offset\+: 0x110 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a6b37c4aeb2d2b387fb79a6af2454d8d3}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!LPTR@{LPTR}}
\index{LPTR@{LPTR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LPTR}{LPTR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a6b37c4aeb2d2b387fb79a6af2454d8d3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+LPTR}

OCTOSPI Low Power Timeout register, Address offset\+: 0x130 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ae83a4795255896d4a015d3526b7df762}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!MID@{MID}}
\index{MID@{MID}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MID}{MID}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ae83a4795255896d4a015d3526b7df762} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+MID}

OCTOPSI HW Magic ID register, Address offset\+: 0x3\+FC \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ac4d100c3a19d687362814b9975f61db5}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!PIR@{PIR}}
\index{PIR@{PIR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PIR}{PIR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ac4d100c3a19d687362814b9975f61db5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+PIR}

OCTOSPI Polling Interval register, Address offset\+: 0x090 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a1bb4b32c85c7d4a2c52dd12fb9fbc8e3}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!PSMAR@{PSMAR}}
\index{PSMAR@{PSMAR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PSMAR}{PSMAR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a1bb4b32c85c7d4a2c52dd12fb9fbc8e3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+PSMAR}

OCTOSPI Polling Status Match register, Address offset\+: 0x088 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_aceec86c14c2af88f8c441a23d27c0c22}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!PSMKR@{PSMKR}}
\index{PSMKR@{PSMKR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PSMKR}{PSMKR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_aceec86c14c2af88f8c441a23d27c0c22} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+PSMKR}

OCTOSPI Polling Status Mask register, Address offset\+: 0x080 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ab4a777b2a2635f47a26ab4328e8d4a85}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ab4a777b2a2635f47a26ab4328e8d4a85} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED}

Reserved, Address offset\+: 0x004 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a1396a146e3c22be923626d604bbce470}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a1396a146e3c22be923626d604bbce470} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}2\mbox{]}}

Reserved, Address offset\+: 0x018-\/0x01C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ab273fcbf40893bb4f213f9c3991a7f86}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED10@{RESERVED10}}
\index{RESERVED10@{RESERVED10}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED10}{RESERVED10}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ab273fcbf40893bb4f213f9c3991a7f86} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED10}

Reserved, Address offset\+: 0x10C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a6027570a8b87a6843d69209f5e08c759}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED11@{RESERVED11}}
\index{RESERVED11@{RESERVED11}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED11}{RESERVED11}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a6027570a8b87a6843d69209f5e08c759} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED11\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x114-\/0x11C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a8a7c7b5da8ab25a785528330a2930d3f}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED12@{RESERVED12}}
\index{RESERVED12@{RESERVED12}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED12}{RESERVED12}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a8a7c7b5da8ab25a785528330a2930d3f} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED12\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x124-\/0x12C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a41c9fec3b5915ebb84e0c65bd0f6112c}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED13@{RESERVED13}}
\index{RESERVED13@{RESERVED13}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED13}{RESERVED13}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a41c9fec3b5915ebb84e0c65bd0f6112c} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED13\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x134-\/0x13C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a4297eefcc58cebb4137aa7aa8b3273e8}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED14@{RESERVED14}}
\index{RESERVED14@{RESERVED14}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED14}{RESERVED14}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a4297eefcc58cebb4137aa7aa8b3273e8} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED14}

Reserved, Address offset\+: 0x144 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a684105027411e5937275840c83618729}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED15@{RESERVED15}}
\index{RESERVED15@{RESERVED15}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED15}{RESERVED15}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a684105027411e5937275840c83618729} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED15}

Reserved, Address offset\+: 0x14C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_aa4f4afe2981ea4f9516428393ffc3b0e}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED16@{RESERVED16}}
\index{RESERVED16@{RESERVED16}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED16}{RESERVED16}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_aa4f4afe2981ea4f9516428393ffc3b0e} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED16\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x154-\/0x15C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a9af5040cff1d5d7cc881da5cf9da79bc}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED17@{RESERVED17}}
\index{RESERVED17@{RESERVED17}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED17}{RESERVED17}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a9af5040cff1d5d7cc881da5cf9da79bc} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED17\mbox{[}7\mbox{]}}

Reserved, Address offset\+: 0x164-\/0x17C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a50e4dd6d85fc5aa3d157c6d101da2ae8}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED18@{RESERVED18}}
\index{RESERVED18@{RESERVED18}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED18}{RESERVED18}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a50e4dd6d85fc5aa3d157c6d101da2ae8} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED18}

Reserved, Address offset\+: 0x184 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a5f9bb07a7f90f6c9629f2c8a0cbcd2ad}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED19@{RESERVED19}}
\index{RESERVED19@{RESERVED19}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED19}{RESERVED19}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a5f9bb07a7f90f6c9629f2c8a0cbcd2ad} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED19}

Reserved, Address offset\+: 0x18C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_af8fcdc41ec1e2b222e804dab9970cd10}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_af8fcdc41ec1e2b222e804dab9970cd10} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}6\mbox{]}}

Reserved, Address offset\+: 0x028-\/0x03C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a4454cd7801f08e319b93153efe6dffa4}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED20@{RESERVED20}}
\index{RESERVED20@{RESERVED20}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED20}{RESERVED20}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a4454cd7801f08e319b93153efe6dffa4} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED20\mbox{[}3\mbox{]}}

Reserved, Address offset\+: 0x194-\/0x19C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_afb0d39d49dab12fb3db244623f8ac0c9}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED21@{RESERVED21}}
\index{RESERVED21@{RESERVED21}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED21}{RESERVED21}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_afb0d39d49dab12fb3db244623f8ac0c9} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED21\mbox{[}23\mbox{]}}

Reserved, Address offset\+: 0x1\+A4-\/0x1\+FC \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a17106bf864619eeb7a9f670e1882681a}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED22@{RESERVED22}}
\index{RESERVED22@{RESERVED22}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED22}{RESERVED22}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a17106bf864619eeb7a9f670e1882681a} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED22\mbox{[}122\mbox{]}}

Reserved, Address offset\+: 0x204-\/0x3\+EC \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a4e57b705fa76a5e8a671d5cbb31e2da8}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED3@{RESERVED3}}
\index{RESERVED3@{RESERVED3}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED3}{RESERVED3}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a4e57b705fa76a5e8a671d5cbb31e2da8} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED3}

Reserved, Address offset\+: 0x044 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a03509b1d3c60ccbb7d1cde25b08fcce8}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED4@{RESERVED4}}
\index{RESERVED4@{RESERVED4}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED4}{RESERVED4}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a03509b1d3c60ccbb7d1cde25b08fcce8} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED4}

Reserved, Address offset\+: 0x04C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_af6839968188cfe826d6672fad77e7be4}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED5@{RESERVED5}}
\index{RESERVED5@{RESERVED5}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED5}{RESERVED5}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_af6839968188cfe826d6672fad77e7be4} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED5\mbox{[}11\mbox{]}}

Reserved, Address offset\+: 0x054-\/0x07C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a1c1eea519097a483369b16d579213b21}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED6@{RESERVED6}}
\index{RESERVED6@{RESERVED6}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED6}{RESERVED6}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a1c1eea519097a483369b16d579213b21} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED6}

Reserved, Address offset\+: 0x084 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a63540ebe30220332fd765f775ffd0aa0}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED7@{RESERVED7}}
\index{RESERVED7@{RESERVED7}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED7}{RESERVED7}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a63540ebe30220332fd765f775ffd0aa0} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED7}

Reserved, Address offset\+: 0x08C \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a534fdd219a20c191e0a451b1b164ee1c}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED8@{RESERVED8}}
\index{RESERVED8@{RESERVED8}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED8}{RESERVED8}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a534fdd219a20c191e0a451b1b164ee1c} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED8\mbox{[}27\mbox{]}}

Reserved, Address offset\+: 0x094-\/0x0\+FC \Hypertarget{struct_o_c_t_o_s_p_i___type_def_aff35db3f551e942d4701624c14554afb}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!RESERVED9@{RESERVED9}}
\index{RESERVED9@{RESERVED9}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED9}{RESERVED9}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_aff35db3f551e942d4701624c14554afb} 
uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+RESERVED9}

Reserved, Address offset\+: 0x104 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_af2d07941b01f96222d175a411a99cbc5}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!SR@{SR}}
\index{SR@{SR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_af2d07941b01f96222d175a411a99cbc5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+SR}

OCTOSPI Status register, Address offset\+: 0x020 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_abd076236680eeed099c89f7443e23880}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!TCR@{TCR}}
\index{TCR@{TCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TCR}{TCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_abd076236680eeed099c89f7443e23880} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+TCR}

OCTOSPI Timing Configuration register, Address offset\+: 0x108 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_adad6a0a30021b2b7277d2ab520767e25}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!VER@{VER}}
\index{VER@{VER}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{VER}{VER}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_adad6a0a30021b2b7277d2ab520767e25} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+VER}

OCTOSPI Version register, Address offset\+: 0x3\+F4 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a5f2343ad009c5df8a20651333a26da6d}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WABR@{WABR}}
\index{WABR@{WABR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WABR}{WABR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a5f2343ad009c5df8a20651333a26da6d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WABR}

OCTOSPI Write Alternate Bytes register, Address offset\+: 0x1\+A0 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a72e85208b55696102636bdf50e58dc98}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WCCR@{WCCR}}
\index{WCCR@{WCCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WCCR}{WCCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a72e85208b55696102636bdf50e58dc98} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WCCR}

OCTOSPI Write Communication Configuration register, Address offset\+: 0x180 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_afd4ca0392882475e1d8ff0461d97362e}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WIR@{WIR}}
\index{WIR@{WIR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WIR}{WIR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_afd4ca0392882475e1d8ff0461d97362e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WIR}

OCTOSPI Write Instruction register, Address offset\+: 0x190 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ac5f058bd9896d8bfc4fa3206d1e1f755}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WPABR@{WPABR}}
\index{WPABR@{WPABR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPABR}{WPABR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ac5f058bd9896d8bfc4fa3206d1e1f755} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WPABR}

OCTOSPI Wrap Alternate Bytes register, Address offset\+: 0x160 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a49e9d597b1d04c06107e6f458a893494}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WPCCR@{WPCCR}}
\index{WPCCR@{WPCCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPCCR}{WPCCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a49e9d597b1d04c06107e6f458a893494} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WPCCR}

OCTOSPI Wrap Communication Configuration register, Address offset\+: 0x140 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_ac83773556b0dc04b2a3bda3820e1a258}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WPIR@{WPIR}}
\index{WPIR@{WPIR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPIR}{WPIR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_ac83773556b0dc04b2a3bda3820e1a258} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WPIR}

OCTOSPI Wrap Instruction register, Address offset\+: 0x150 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_acc4f24b481b265e2b9e1de1cdbcc7010}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WPTCR@{WPTCR}}
\index{WPTCR@{WPTCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPTCR}{WPTCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_acc4f24b481b265e2b9e1de1cdbcc7010} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WPTCR}

OCTOSPI Wrap Timing Configuration register, Address offset\+: 0x148 \Hypertarget{struct_o_c_t_o_s_p_i___type_def_a8386b6515a1abf5b6c01506469779695}\index{OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}!WTCR@{WTCR}}
\index{WTCR@{WTCR}!OCTOSPI\_TypeDef@{OCTOSPI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WTCR}{WTCR}}
{\footnotesize\ttfamily \label{struct_o_c_t_o_s_p_i___type_def_a8386b6515a1abf5b6c01506469779695} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t OCTOSPI\+\_\+\+Type\+Def\+::\+WTCR}

OCTOSPI Write Timing Configuration register, Address offset\+: 0x188 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
